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<h1 class="sectionedit1"><a name="vhdl_netlister_readme" id="vhdl_netlister_readme">VHDL netlister README</a></h1>
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<pre class="code">The VHDL backend

Written by Magnus Danielson and improved by Thomas Heidel 


A few things you have to care about:

1. In order to generate valid component declarations, you
   have to add an additional attribute to each pin.
   &quot;type=IN&quot; or &quot;type=OUT&quot; or &quot;type=INOUT&quot;

2. The &quot;device&quot; attribute must be unique to a symbol!
   The verilog symbols of the same type for example, have all
   the same device attribute and will therefore not work.

3. Make sure your component-library picks up the vhdl symbols instead
   of the verilog symbols  Library paths that show up last are searched
   first!</pre>

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